Kiran Kariyannavar
Graz
Summary
Diligent engineer with 17+ years of experience in SoC digital design, verification, and DfT
Overview
19
19
years of professional experience
Work History
SoC Digital Design Engineer
NXP Semiconductors
Graz, Austria
01.2022 - Current
- - RTL implementation & verification for secure automotive SoCs
- - Developed digital IPs (Clock/Reset controller, FRO recalibration, XTAL controller)
- - Spyglass Lint/CDC/DFT checks, Sub System & IC level simulations
- - Collaboration with system, verification, backend teams
Visiting Lecturer
FH Joanneum
Graz, Austria
03.2020 - Current
- - Teaching Test Standards and DfT methodologies
DfT Engineer / Architect
NXP Semiconductors
Graz, Austria
09.2012 - 01.2022
- - DfT RTL implementation, scan insertion, ATPG (Stuck-at, Transition, Path Delay)
- - Mixed-signal test integration (CTAG.AMS), secure memory access validation
- - Silicon bring-up & test optimization
ASIC Design Engineer
Ericsson AB
Stockholm, Sweden
10.2011 - 08.2012
- - Analog front-end design for human body communication
- - Demonstrations at ECCTD 2011 and CES 2012
SoC Verification & DfT Engineer
Wipro Technologies
Bangalore, India
08.2006 - 08.2009
- - Verification of automotive SoCs (GPIO, SPI, PLL)
- - Scan insertion, LBIST, Boundary Scan for TI Houston & NEC Japan projects
Education
MSc - System-on-Chip
01.2012
GPA: 4.2/5
B.Tech - Electronics & Communication Engineering
01.2006
GPA: 74.68%
Skills
- Digital Design & Verification: SystemVerilog, Verilog, VHDL, low-power design
- DfT & Test: Scan insertion, ATPG, LBIST, MBIST, Boundary Scan, Mixed-Signal Test
- Tools: Synopsys (DFTMAX, Tetramax, PrimeTime, VCS, Design Compiler), Cadence (Genus, Conformal, Virtuoso, irun), Mentor/Siemens (Tessent, TestKompress, Modelsim), Spyglass (Lint, CDC, RDC, DFT)
- Automation & Scripting: Python, Perl, Tcl
Languages
English – C1 Advanced
German – B1
Achievements & Patents
- US Patent 9385818 – Handling of signals transmitted through a human body
- PCT Patent SE PCT/SE2012/050058 – Adaptive Manchester Decoder for Narrowband Pulse Communication
- President, Electronics & Communications Association (NIE, India)
- Sportsman of the Year, Honnavar, India
Timeline
SoC Digital Design Engineer - NXP Semiconductors
01.2022 - Current
Visiting Lecturer - FH Joanneum
03.2020 - Current
DfT Engineer / Architect - NXP Semiconductors
09.2012 - 01.2022
ASIC Design Engineer - Ericsson AB
10.2011 - 08.2012
SoC Verification & DfT Engineer - Wipro Technologies
08.2006 - 08.2009
NIE Mysore - B.Tech, Electronics & Communication Engineering
Linköping University - MSc, System-on-Chip