Uma Kulkarni
Analog Mixed-Signal And RF Verification Engineer
Linz,4
Summary
Verification engineer capable of handling a full chip verification activity taking care of all domains ranging from RF, analog, AMS and digital. Good amount of experience in handling interfaces between exerts from different domains. My skills make me capable of being a full chip or system owner.
Overview
23
23
years of professional experience
7
7
years of post-secondary education
Work History
AMS Design and Verification Engineer
Infineon Technologies
01.2024 - Current
Analog Design and Verification Engineer
Infineon Technologies
10.2021 - 01.2024
Working Student, Analog Circuit Design
Apple
01.2021 - 09.2021
PhD Student
Christian Doppler Labs, JKU
3 2019 - 12.2020
Working Student
Intel
02.2018 - 02.2019
Research scholar
International Institute of Information Technology
06.2015 - 06.2017
Senior Design Engineer
Innovaide Consulting Services
03.2014 - 02.2015
Senior Design Engineer
ARF Design
12.2012 - 02.2014
Senior Digital Design Engineer
Texas Instruments India Private Limited
04.2004 - 05.2009
VLSI Engineer
Wipro Technologies Private Limited
04.2001 - 03.2004
Education
Master of Science (By Research) - Electronic System Design -
International Institute of Information Technology
Bangalore, India 08.2015 - 05.2018
Post-Graduate Diploma in VLSI Design -
Advance Computing Training School (CDAC-ACTS)
Pune, India 10.2000 - 05.2001
Bachelor of Engineering - Electronics and Communication -
Pune University
Pune, India 09.1996 - 05.2000
Skills
- Skills across different functions of chip design
- 4 years experience in analog mixed signal design and verification
- Hands-on experience in digital, analog and RF circuit design
- Impeccable problem solving attitude to narrow down area of issue
- Good expertise in handling interface across functions of chip design
- Pre-silicon verification experience spanning across digital, AMS, analog and RF domain
Areasofknowledge
C, SystemC, Verilog, VerilogA, Verilog AMS, VHDL, Cadence Virtuoso Framework, Synopsys VCS, NCSim
Personal Information
- Date of Birth: 02/02/79
- Nationality: Indian
Publications
A Systematic Approach to Determining the Weights of the Capacitors in the DAC of Non-binary Redundant SAR ADCs, 31st International Conference on VLSI Design, Jan 2018
Languages
Marathi
Native language
English
Proficient
C2
Interests
Running, strength training, cooking, meditation
Timeline
AMS Design and Verification Engineer
Infineon Technologies
01.2024 - Current
Analog Design and Verification Engineer
Infineon Technologies
10.2021 - 01.2024
Working Student, Analog Circuit Design
Apple
01.2021 - 09.2021
Working Student
Intel
02.2018 - 02.2019
Master of Science (By Research) - Electronic System Design -
International Institute of Information Technology
08.2015 - 05.2018
Research scholar
International Institute of Information Technology
06.2015 - 06.2017
Senior Design Engineer
Innovaide Consulting Services
03.2014 - 02.2015
Senior Design Engineer
ARF Design
12.2012 - 02.2014
Senior Digital Design Engineer
Texas Instruments India Private Limited
04.2004 - 05.2009
VLSI Engineer
Wipro Technologies Private Limited
04.2001 - 03.2004
Post-Graduate Diploma in VLSI Design -
Advance Computing Training School (CDAC-ACTS)
10.2000 - 05.2001
Bachelor of Engineering - Electronics and Communication -
Pune University
09.1996 - 05.2000
PhD Student
Christian Doppler Labs, JKU
3 2019 - 12.2020
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